View VS1011E_3092411.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

VS1011E vs1011 e VS1011E - mpeg audio codec features 2 decodes mpeg 1.0 & 2.0 audio layer iii (cbr, vbr, abr); layers i & ii optional; wav (pcm + ima adpcm) 2 320 kbit/s mp3 with 12.0 mhz external clock 2 streaming support for mp1/2/3 and wav 2 bass and treble controls 2 operates with single 12..13 mhz or 24..26 mhz external clock 2 internal clock doubler 2 low-power operation 2 high-quality stereo dac with no phase er- ror between channels 2 stereo earphone driver capable of driving a 30 load 2 separate 2.5 .. 3.6 v operating voltages for analog and digital 2 serial control and data interfaces 2 can be used as a slave co-processor 2 5.5 kib on-chip ram for user code / data 2 spi ?ash boot for special applications 2 new functions may be added with software and 4 gpio pins 2 lead-free and rohs-compliant packages lpqfp-48, bga-49, and soic-28 description VS1011E is a single-chip mpeg audio decoder. the chip contains a high-performance, low-power dsp processor core vs dsp 4 , working memory, 5 kib instruction ram and 0.5 kib data ram for user applications, serial control and input data interfaces, 4 general purpose i/o pins, as well as a high-quality variable-sample-rate stereo dac, followed by an earphone ampli?er and a common buffer. VS1011E receives its input bitstream through a se- rial input bus, which it listens to as a system slave. the input stream is decoded and passed through a digital volume control to an 18-bit oversampling, multi-bit, sigma-delta dac. the decoding is con- trolled via a serial control bus. in addition to basic decoding, it is possible to add application speci?c features, like dsp effects, to the user ram mem- ory. version 1.04, 2007-10-08 1 vlsi solution y instruction ram instruction rom stereo dac lr stereo ear?phone driver audiooutput x romx ram y rom y ram vsdsp 4 serialdata/ control interface dreqso si sclk xcs vs1011 gpio 4 gpio xdcs
VS1011E vs1011 e contents contents 1 license 8 2 disclaimer 8 3 de?nitions 8 4 characteristics & speci?cations 9 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.3 analog characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.4 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.5 digital characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.6 switching characteristics - boot initialization . . . . . . . . . . . . . . . . . . . . . . . 11 5 packages and pin descriptions 12 5.1 packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.1 lqfp-48 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1.2 bga-49 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1.3 soic-28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.2.1 lqfp-48 and bga-49 pin descriptions . . . . . . . . . . . . . . . . . . . . . . 14 5.2.2 soic-28 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 connection diagram, lqfp-48 16 7 spi buses 17 version 1.04, 2007-10-08 2 vlsi solution y
VS1011E vs1011 e contents 7.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.2 spi bus pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.2.1 vs1002 native modes (new mode) . . . . . . . . . . . . . . . . . . . . . . . . 17 7.2.2 vs1001 compatibility mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.3 serial protocol for serial data interface (sdi) . . . . . . . . . . . . . . . . . . . . . . . 18 7.3.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3.2 sdi in vs1002 native modes (new mode) . . . . . . . . . . . . . . . . . . . . 18 7.3.3 sdi in vs1001 compatibility mode . . . . . . . . . . . . . . . . . . . . . . . . 18 7.4 data request pin dreq . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.5 serial protocol for serial command interface (sci) . . . . . . . . . . . . . . . . . . . . 19 7.5.1 general . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.5.2 sci read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.5.3 sci write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.6 spi timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.7 spi examples with sm sdinew and sm sdishared set . . . . . . . . . . . . . . . 23 7.7.1 two sci writes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.7.2 two sdi bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.7.3 sci operation in middle of two sdi bytes . . . . . . . . . . . . . . . . . . . . 24 8 functional description 25 8.1 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2 supported audio codecs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.2.1 supported mp1 (mpeg layer i) formats . . . . . . . . . . . . . . . . . . . . . 25 8.2.2 supported mp2 (mpeg layer ii) formats . . . . . . . . . . . . . . . . . . . . . 26 8.2.3 supported mp3 (mpeg layer iii) formats . . . . . . . . . . . . . . . . . . . . 26 version 1.04, 2007-10-08 3 vlsi solution y
VS1011E vs1011 e contents 8.2.4 supported riff wav formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8.3 data flow of VS1011E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.4 serial data interface (sdi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.5 serial control interface (sci) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.6 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.6.1 sci mode (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8.6.2 sci status (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.6.3 sci bass (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.6.4 sci clockf (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.6.5 sci decode time (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.6.6 sci audata (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.6.7 sci wram (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.6.8 sci wramaddr (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.6.9 sci hdat0 and sci hdat1 (r) . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.6.10 sci aiaddr (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.6.11 sci vol (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.6.12 sci aictrl[x] (rw) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 operation 36 9.1 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.2 hardware reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.3 software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 9.4 spi boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.5 play/decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.6 feeding pcm data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 version 1.04, 2007-10-08 4 vlsi solution y
VS1011E vs1011 e contents 9.7 sdi tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 9.7.1 sine test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.7.2 pin test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.7.3 memory test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 9.7.4 sci test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10 VS1011E registers 40 10.1 who needs to read this chapter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.2 the processor core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.3 VS1011E memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.4 sci registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.5 serial data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.6 dac registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.7 gpio registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.8 interrupt registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.9 system vector tags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.9.1 audioint, 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.9.2 sciint, 0x21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.9.3 dataint, 0x22 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.9.4 usercodec, 0x0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.10system vector functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.10.1 writeiram(), 0x2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.10.2 readiram(), 0x4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.10.3 databytes(), 0x6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.10.4 getdatabyte(), 0x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 version 1.04, 2007-10-08 5 vlsi solution y
VS1011E vs1011 e contents 10.10.5 getdatawords(), 0xa . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 11 vs1011 version changes 47 11.1 changes between vs1011b and VS1011E, 2005-07-13 . . . . . . . . . . . . . . . . . . 47 11.2 migration checklist from vs1011b to VS1011E, 2005-07-13 . . . . . . . . . . . . . . . 47 12 document version changes 48 12.1 version 1.04 for VS1011E, 2007-10-08 . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.2 version 1.03 for VS1011E, 2005-09-05 . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.3 version 1.02 for VS1011E, 2005-07-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.4 version 1.01 for vs1011b, 2004-11-19 . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.5 version 1.00 for vs1011b, 2004-10-22 . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.6 version 0.71 for vs1011, 2004-07-20 . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.7 version 0.70 for vs1011, 2004-05-13 . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 12.8 version 0.62 for vs1011, 2004-03-24 . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 13 contact information 49 version 1.04, 2007-10-08 6 vlsi solution y
VS1011E vs1011 e list of figures list of figures 1 pin con?guration, lqfp-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2 pin con?guration, bga-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 pin con?guration, soic-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4 typical connection diagram using lqfp-48. . . . . . . . . . . . . . . . . . . . . . . . 16 5 bsync signal - one byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6 bsync signal - two byte transfer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 sci word read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8 sci word write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 spi timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 two sci operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 11 two sdi bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 12 two sdi bytes separated by an sci operation. . . . . . . . . . . . . . . . . . . . . . . 24 13 data flow of VS1011E. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 14 users memory map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 version 1.04, 2007-10-08 7 vlsi solution y
VS1011E vs1011 e 1. license 1 license mpeg layer-3 audio decoding technology licensed from fraunhofer iis and thomson. note: if you enable layer i and layer ii decoding, you are liable for any patent issues that may arise from using these formats. joint licensing of mpeg 1.0 / 2.0 layer iii does not cover all patents pertaining to layers i and ii. 2 disclaimer all properties and ?gures are subject to change. 3 de?nitions b byte, 8 bits. b bit. ki kibi = 2 10 = 1024 (iec 60027-2). mi mebi = 2 20 = 1048576 (iec 60027-2). vs dsp vlsi solutions dsp core. w word. in vs dsp, instruction words are 32-bit and data words are 16-bit wide. version 1.04, 2007-10-08 8 vlsi solution y
VS1011E vs1011 e 4. characteristics & specifications 4 characteristics & speci?cations 4.1 absolute maximum ratings parameter symbol min max unit analog positive supply avdd -0.3 3.6 v digital positive supply dvdd -0.3 3.6 v current at any digital output 50 ma voltage at any digital input dgnd-1.0 dvdd+1.0 1 v operating temperature -30 +85 c functional operating temperature -40 +95 c storage temperature -65 +150 c 1 must not exceed 3.6 v 4.2 recommended operating conditions parameter symbol min typ max unit ambient operating temperature -40 +85 c analog and digital ground 1 agnd dgnd 0.0 v positive analog avdd 2.5 2.7 3.6 v positive digital dvdd 2.3 2.5 3.6 v input clock frequency xtali 24 24.576 26 mhz input clock frequency, with clock doubler xtali 12 12.288 13 mhz internal clock frequency clki 24 2 24.576 26 mhz master clock duty cycle 40 50 60 % 1 must be connected together as close to the device as possible for latch-up immunity. 2 the maximum sample rate that can be played with correct speed is clki/512. thus, if clki is 24 mhz, 48 khz sample rate is played 2.5% off-key. version 1.04, 2007-10-08 9 vlsi solution y
VS1011E vs1011 e 4. characteristics & specifications 4.3 analog characteristics unless otherwise noted: avdd=2.5..3.6v, dvdd=2.3..3.6v, ta=-40..+85 c, xtali=12..13mhz, internal clock doubler active. dac tested with 1307.894 hz full-scale output sinewave, measurement bandwidth 20..20000 hz, analog output load: left to gbuf 30 , right to gbuf 30 . parameter symbol min typ max unit dac resolution 18 bits total harmonic distortion thd 0.1 0.2 % dynamic range (dac unmuted, a-weighted) idr 90 db s/n ratio (full scale signal) snr 70 85 db interchannel isolation (cross talk) 50 75 db interchannel isolation (cross talk), with gbuf 40 db interchannel gain mismatch -0.5 0.5 db frequency response -0.1 0.1 db full scale output voltage (peak-to-peak) 1.4 1.6 1 2.0 vpp deviation from linear phase 5 analog output load resistance aolr 16 30 2 analog output load capacitance 100 pf 1 3.2 volts can be achieved with +-to-+ wiring for mono difference sound. 2 aolr may be much lower, but below typical distortion performance may be compromised. 4.4 power consumption average current tested with an mpeg 1.0 layer iii 128 kbit/s sample and generated sine, output at full volume, xtali = 12.288 mhz, internal clock doubler enabled, dvdd = 2.5 v, avdd = 2.7 v. parameter min typ max unit power supply consumption avdd, reset 0.5 30 1 a power supply consumption dvdd, reset 1 30 1 a power supply consumption avdd, sine test, 30 20 ma power supply consumption avdd, sine test, 30 + gbuf 39 50 ma power supply consumption dvdd, sine test 8 17 ma power supply consumption avdd, no load 6 ma power supply consumption avdd, output load 30 10 ma power supply consumption avdd, 30 + gbuf 16 ma power supply consumption dvdd 16 ma version 1.04, 2007-10-08 10 vlsi solution y
VS1011E vs1011 e 4. characteristics & specifications 4.5 digital characteristics parameter symbol min typ max unit high-level input voltage 0 : 7 dvdd dvdd+0.3 1 v low-level input voltage -0.2 0 : 3 dvdd v high-level output voltage at i o = -2.0 ma 0 : 7 dvdd v low-level output voltage at i o = 2.0 ma 0 : 3 dvdd v input leakage current -1.0 1.0 1 a spi input clock frequency 2 clki 6 mhz rise time of all output pins, load = 50 pf 50 ns 1 must not exceed 3.6v 2 value for sci reads. sci and sdi writes allow clki 4 . 4.6 switching characteristics - boot initialization parameter symbol min max unit xreset active time 2 xtali xreset inactive to software ready 50000 1 xtali power on reset, rise time of dvdd 10 v/s 1 dreq rises when initialization is complete. you should not send any data or commands before that. version 1.04, 2007-10-08 11 vlsi solution y
VS1011E vs1011 e 5. packages and pin descriptions 5 packages and pin descriptions 5.1 packages both lpqfp-48 and bga-49 are lead (pb) free and also rohs compliant packages. rohs is a short name of directive 2002/95/ec on the restriction of the use of certain hazardous substances in electrical and electronic equipment . soic-28 is a lead-free rohs-compliant package starting from VS1011E. 5.1.1 lqfp-48 figure 1: pin con?guration, lqfp-48. lqfp-48 package dimensions are at http://www.vlsi.?/ . version 1.04, 2007-10-08 12 vlsi solution y 1 48
VS1011E vs1011 e 5. packages and pin descriptions 5.1.2 bga-49 figure 2: pin con?guration, bga-49. bga-49 package dimensions are at http://www.vlsi.?/ . 5.1.3 soic-28 figure 3: pin con?guration, soic-28. soic-28 package dimensions are at http://www.vlsi.?/ . version 1.04, 2007-10-08 13 vlsi solution y a bc d e f g 1 2 3 4 5 6 7 top view 0.80 typ 4.807.00 1.10 ref 0.80 typ 1.10 ref 4.807.00 a1 ball pad corner soic ? 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15 16 17 18 19 20 21 22 23 27 28 26 24 25
VS1011E vs1011 e 5. packages and pin descriptions 5.2 pin descriptions 5.2.1 lqfp-48 and bga-49 pin descriptions pin name lqfp- 48 pin bga49 ball pin type function xreset 3 b1 di active low asynchronous reset, schmitt-triggered dgnd0 4 d2 pwr digital ground dvdd0 6 d3 pwr digital power supply dreq 8 e2 do data request, input bus gpio2 2 / dclk 1 9 e1 di general purpose io 2 / serial input data bus clock gpio3 2 / sdata 1 10 f2 di general purpose io 3 / serial data input xdcs 4 / bsync 1 13 e3 di data chip select / byte sync, connect to dvdd if not used dvdd1 14 f3 pwr digital power supply dgnd1 16 f4 pwr digital ground xtalo 17 g3 ao crystal output xtali 18 e4 ai crystal input dvdd2 19 g4 pwr digital power supply dgnd2 20 f5 pwr digital ground (in bga-49, dgnd2, 3, 4 conn. together) dgnd3 21 g5 pwr digital ground dgnd4 22 f6 pwr digital ground xcs 4 23 g6 di chip select input (active low) sclk 2 28 d6 di clock for serial bus si 2 29 e7 di serial input so 30 d5 do3 serial output, active when xcs=0, regardless of xreset test 32 c6 di reserved for test, connect to dvdd gpio0 / spiboot 2 ; 3 33 c7 dio general purpose io 0, use 100 k pull-down resistor gpio1 2 34 b6 dio general purpose io 1 agnd0 37 c5 pwr analog ground, low-noise reference avdd0 38 b5 pwr analog power supply right 39 a6 ao right channel output agnd1 40 b4 pwr analog ground agnd2 41 a5 pwr analog ground gbuf 42 c4 ao common buffer for headphones avdd1 43 a4 pwr analog power supply rcap 44 b3 aio ?ltering capacitance for reference avdd2 45 a3 pwr analog power supply left 46 b2 ao left channel output agnd3 47 a2 pwr analog ground 1 first pin function is active in new mode, latter in compatibility mode. 2 if not used, use 100 k pull-down resistor. 3 use 100 k pull-down resistor. if pull-up is used instead, spi boot is tried. see chapter 9.4 for details. 4 if not used, use 100 k pull-up resistor. pin types: type description di digital input, cmos input pad do digital output, cmos input pad dio digital input/output do3 digital output, cmos tri-stated output pad type description ai analog input ao analog output aio analog input/output pwr power supply pin in bga-49, no-connect balls are a1, a7, b7, c1, c2, c3, d1, d4, d7, e5, e6, f1, f7, g1, g2, g7. in lqfp-48, no-connect pins are 1, 2, 5, 7, 11, 12, 15, 24, 25, 26, 27, 31, 35, 36, 48. version 1.04, 2007-10-08 14 vlsi solution y
VS1011E vs1011 e 5. packages and pin descriptions 5.2.2 soic-28 pin descriptions pin name pin pin type function dreq 1 do data request, input bus gpio2 2 / dclk 1 2 dio serial input data bus clock gpio3 2 / sdata 1 3 di serial data input xdcs 4 / bsync 1 4 di byte synchronization signal dvdd1 5 pwr digital power supply dgnd1 6 pwr digital ground xtalo 7 clk crystal output xtali 8 clk crystal input dvdd2 9 pwr digital power supply dgnd2 10 pwr digital ground xcs 4 11 di chip select input (active low) sclk 2 12 di clock for serial bus si 2 13 di serial input so 14 do3 serial output, active when xcs=0, regardless of xreset test 15 di reserved for test, connect to dvdd gpio0 / spiboot 2 ; 3 16 dio general purpose io 0, use 100 k pull-down resistor gpio1 2 17 dio general purpose io 1 agnd0 18 pwr analog ground avdd0 19 pwr analog power supply right 20 ao right channel output agnd2 21 pwr analog ground rcap 22 aio ?ltering capacitance for reference avdd2 23 pwr analog power supply left 24 ao left channel output agnd3 25 pwr analog ground xreset 26 di active low asynchronous reset dgnd0 27 pwr digital ground dvdd0 28 pwr digital power supply 1 first pin function is active in new mode, latter in compatibility mode. 2 if not used, use 100 k pull-down resistor. 3 use 100 k pull-down resistor. if pull-up is used instead, spi boot is tried. see chapter 9.4 for details. 4 if not used, use 100 k pull-up resistor. pin types: type description di digital input, cmos input pad do digital output, cmos input pad dio digital input/output do3 digital output, cmos tri-stated output pad type description ai analog input ao analog output aio analog input/output pwr power supply pin version 1.04, 2007-10-08 15 vlsi solution y
VS1011E vs1011 e 6. connection diagram, lqfp-48 6 connection diagram, lqfp-48 figure 4: typical connection diagram using lqfp-48. the common buffer gbuf can be used for common voltage (1.23 v) for earphones. this will eliminate the need for large isolation capacitors on line outputs, and thus the audio output pins from VS1011E may be connected directly to the earphone connector. if gbuf is not used, left and right must be provided with 1-100 1 f capacitors depending on load resistance. note: this connection assumes sm sdinew is active (see chapter 8.6.1). if also sm sdishare is used, xdcs should have a pull-up resistor (see chapter 7.2.1). version 1.04, 2007-10-08 16 vlsi solution y
VS1011E vs1011 e 7. spi buses 7 spi buses 7.1 general the spi bus - that was originally used in some motorola devices - has been used for both VS1011Es serial data interface sdi (chapters 7.3 and 8.4) and serial control interface sci (chapters 7.5 and 8.5). 7.2 spi bus pin descriptions 7.2.1 vs1002 native modes (new mode) these modes are active on VS1011E when sm sdinew is set to 1. dclk and sdata are not used for data transfer and they can be used as general-purpose i/o pins (gpio2 and gpio3). bsync function changes to data interface chip select (xdcs). sdi pin sci pin description xdcs xcs active low chip select input. a high level forces the serial interface into standby mode, ending the current operation. a high level also forces serial output (so) to high impedance state. if sm sdishare is 1, pin xdcs is not used, but the signal is generated internally by inverting xcs. sck serial clock input. the serial clock is also used internally as the master clock for the register interface. sck can be gated or continuous. in either case, the ?rst rising clock edge after xcs has gone low marks the ?rst bit to be written. si serial input. if a chip select is active, si is sampled on the rising clk edge. - so serial output. in reads, data is shifted out on the falling sck edge. in writes so is at a high impedance state. 7.2.2 vs1001 compatibility mode this mode is active when sm sdinew is 0 (default). in this mode, dclk, sdata and bsync are active. version 1.04, 2007-10-08 17 vlsi solution y
VS1011E vs1011 e 7. spi buses sdi pin sci pin description - xcs active low chip select input. a high level forces the serial interface into standby mode, ending the current operation. a high level also forces serial output (so) to high impedance state. there is no chip select for sdi, which is always active. bsync - sdi data is synchronized with a rising edge of bsync. dclk sck serial clock input. the serial clock is also used internally as the master clock for the register interface. sck can be gated or continuous. in either case, the ?rst rising clock edge after xcs has gone low marks the ?rst bit to be written. sdata si serial input. si is sampled on the rising sck edge, if xcs is low. - so serial output. in reads, data is shifted out on the falling sck edge. in writes so is at a high impedance state. 7.3 serial protocol for serial data interface (sdi) 7.3.1 general the serial data interface operates in slave mode so the dclk signal must be generated by an external circuit. data (sdata signal) can be clocked in at either the rising or falling edge of dclk (chapter 8.6). VS1011E assumes its data input to be byte-sychronized. sdi bytes may be transmitted either msb or lsb ?rst, depending of contents of sci mode (chapter 8.6). 7.3.2 sdi in vs1002 native modes (new mode) in vs1002 native modes (which are available also in VS1011E), byte synchronization is achieved by xdcs (or xcs if sm sdishare is 1). the state of xdcs (or xcs) may not change while a data byte transfer is in progress. to always maintain data synchronization even if there may be glitches in the boards using VS1011E, it is recommended to turn xdcs (or xcs) every now and then, for instance once after every ?ash data block or a few kilobytes, just to keep sure the host and VS1011E are in sync. for new designs, using vs1002 native modes are recommended, as they are easier to implement than bsync generation. 7.3.3 sdi in vs1001 compatibility mode when VS1011E is running in vs1001 compatibility mode, a bsync signal must be generated to ensure correct bit-alignment of the input bitstream. the ?rst dclk sampling edge (rising or falling, depending on selected polarity), during which the bsync is high, marks the ?rst bit of a byte (lsb, if lsb-?rst version 1.04, 2007-10-08 18 vlsi solution y
VS1011E vs1011 e 7. spi buses figure 5: bsync signal - one byte transfer. order is used, msb, if msb-?rst order is used). if bsync is 1 when the last bit is received, the receiver stays active and next 8 bits are also received. figure 6: bsync signal - two byte transfer. using vs1001 compatibility mode in new designs is strongly discouraged. 7.4 data request pin dreq the dreq pin/signal is used to signal if VS1011Es fifo is capable of receiving data. if dreq is high, VS1011E can take at least 32 bytes of sdi data or one sci command. when these criteria are not met, dreq is turned low, and the sender should stop transferring new data. because of a 32-byte safety area, the sender may send upto 32 bytes of sdi data at a time without checking the status of dreq, making controlling VS1011E easier for low-speed microcontrollers. note: dreq may turn low or high at any time, even during a byte transmission. thus, dreq should only be used to decide whether to send more bytes. it should not abort a transmission that has already started. note: in vs10xx products upto vs1002, dreq was only used for sdi. in VS1011E dreq is also used to tell the status of sci. 7.5 serial protocol for serial command interface (sci) 7.5.1 general the serial bus protocol for the serial command interface sci (chapter 8.5) consists of an instruction byte, address byte and one 16-bit data word. each read or write operation can read or write a single register. data bits are read at the rising clock edge, so the user should update data at the falling clock edge. bytes are always sent msb ?rrst. version 1.04, 2007-10-08 19 vlsi solution y bsyncsdata dclk d7 d6 d5 d4 d3 d2 d1 d0 bsync sdata dclk d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0
VS1011E vs1011 e 7. spi buses the operation is speci?ed by an 8-bit instruction opcode. the supported instructions are read and write. see table below. instruction name opcode operation read 0000 0011 read data write 0000 0010 write data note: VS1011E sets dreq low after each sci operation. the duration depends on the operation. it is not allowed to start a new sci/sdi operation before dreq is high again. version 1.04, 2007-10-08 20 vlsi solution y
VS1011E vs1011 e 7. spi buses 7.5.2 sci read figure 7: sci word read VS1011E registers are read by the following sequence, as shown in figure 7. first, xcs line is pulled low to select the device. then the read opcode (0x3) is transmitted via the si line followed by an 8-bit word address. after the address has been read in, any further data on si is ignored. the 16-bit data corresponding to the received address will be shifted out onto the so line. xcs should be driven high after data has been shifted out. dreq is driven low for a short while when in a read operation by the chip. this is a very short time and doesnt require special user attention. 7.5.3 sci write figure 8: sci word write VS1011E registers are written to using the following sequence, as shown in figure 8. first, xcs line is pulled low to select the device. then the write opcode (0x2) is transmitted via the si line followed by an 8-bit word address. version 1.04, 2007-10-08 21 vlsi solution y 0 1 2 3 4 5 6 7 8 9 10 11 12 13 30 31 14 15 16 17 0 0 0 0 0 0 1 1 0 0 0 0 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 14 1 0 x instruction (read) address data out xcssck si so don't care don't care dreq execution 0 1 2 3 4 5 6 7 8 9 10 11 12 13 30 31 14 15 16 17 0 0 0 0 0 0 1 0 0 0 0 3 2 1 0 1 0 x address xcssck si 15 14 data out 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 so 0 0 0 0 x 0 instruction (write) dreq execution
VS1011E vs1011 e 7. spi buses after the word has been shifted in and the last clock has been sent, xcs should be pulled high to end the write sequence. after the last bit has been sent, dreq is driven low for the duration of the register update, marked exe- cution in the ?gure. the time varies depending on the register and its contents (see table in chapter 8.6 for details). if the maximum time is longer than what it takes from the microcontroller to feed the next sci command or sdi byte, it is not allowed to ?nish a new sci/sdi operation before dreq has risen up again. 7.6 spi timing diagram figure 9: spi timing diagram. symbol min max unit txcss 5 ns tsu -26 ns th 2 xtali cycles tz 0 ns twl 2 xtali cycles twh 2 xtali cycles tv 2 (+ 25ns 1 ) xtali cycles txcsh -26 ns txcs 2 xtali cycles tdis 10 ns 1 25ns is when pin loaded with 100pf capacitance. the time is shorter with lower capacitance. note: as twl and twh, as well as th require at least 2 clock cycles, the maximum speed for the spi bus that can be used for read operations is 1/6 of VS1011Es external clock speed xtali. for write operations maximum speed is 1/4 of xtali. note: negative numbers mean that the signal can change in different order from what is shown in the diagram. version 1.04, 2007-10-08 22 vlsi solution y xcssck si so 0 1 15 14 16 txcss txcsh twl twh th tsu tv tz tdis txcs 30 31
VS1011E vs1011 e 7. spi buses 7.7 spi examples with sm sdinew and sm sdishared set 7.7.1 two sci writes figure 10: two sci operations. figure 10 shows two consecutive sci operations. note that xcs must be raised to inactive state between the writes. also dreq must be respected as shown in the ?gure. 7.7.2 two sdi bytes figure 11: two sdi bytes. sdi data is synchronized with a raising edge of xcs as shown in figure 11. however, every byte doesnt need separate synchronization. version 1.04, 2007-10-08 23 vlsi solution y 0 1 2 3 30 31 1 0 1 0 0 0 0 0 0 0 x x xcs scksi 2 32 33 61 62 63 sci write 1 sci write 2 dreq dreq up before finishing next sci write 1 2 3 xcs scksi 7 6 5 4 3 1 0 7 6 5 2 1 0 x sdi byte 1 sdi byte 2 0 6 7 8 9 13 14 15 dreq
VS1011E vs1011 e 7. spi buses 7.7.3 sci operation in middle of two sdi bytes figure 12: two sdi bytes separated by an sci operation. figure 12 shows how an sci operation is embedded in between sdi operations. xcs edges are used to synchronize both sdi and sci. remember to respect dreq as shown in the ?gure. version 1.04, 2007-10-08 24 vlsi solution y 0 1 xcs scksi 7 7 6 5 1 0 0 0 7 6 5 1 0 sdi byte sci operation sdi byte 8 9 39 40 41 46 47 x dreq high before end of next transfer dreq
VS1011E vs1011 e 8. functional description 8 functional description 8.1 main features VS1011E is based on a proprietary digital signal processor, vs dsp. it contains all the code and data memory needed for mpeg, wav pcm and wav ima adpcm audio decoding, together with serial interfaces, a multirate stereo audio dac and analog output ampli?ers and ?lters. VS1011E can play all mpeg 1.0, and 2.0 layer i, ii and iii ?les, as well as mpeg 2.5 layer iii ?les, with all sample rates and bitrates, including variable bitrate (vbr) for layer iii. note, that decoding of layers i and ii must be activated separately. 8.2 supported audio codecs conventions mark description + format is supported - format exists but is not supported ? format not tested format doesnt exist 8.2.1 supported mp1 (mpeg layer i) formats mpeg 1.0: samplerate / hz bitrate / kbit/s 32 64 96 128 160 192 224 256 288 320 352 384 416 448 48000 + + + + + + + + + + + + + + 44100 + + + + + + + + + + + + + + 32000 + + + + + + + + + + + + + + mpeg 2.0: samplerate / hz bitrate / kbit/s 32 48 56 64 80 96 112 128 144 160 176 192 224 256 24000 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 22050 ? ? ? ? ? ? ? ? ? ? ? ? ? ? 16000 ? ? ? ? ? ? ? ? ? ? ? ? ? ? version 1.04, 2007-10-08 25 vlsi solution y
VS1011E vs1011 e 8. functional description 8.2.2 supported mp2 (mpeg layer ii) formats mpeg 1.0: samplerate / hz bitrate / kbit/s 32 48 56 64 80 96 112 128 160 192 224 256 320 384 48000 + + + + + + + + + + + + + + 44100 + + + + + + + + + + + + + + 32000 + + + + + + + + + + + + + + mpeg 2.0: samplerate / hz bitrate / kbit/s 8 16 24 32 40 48 56 64 80 96 112 128 144 160 24000 + + + + + + + + + + + + + + 22050 + + + + + + + + + + + + + + 16000 + + + + + + + + + + + + + + 8.2.3 supported mp3 (mpeg layer iii) formats mpeg 1.0 1 : samplerate / hz bitrate / kbit/s 32 40 48 56 64 80 96 112 128 160 192 224 256 320 48000 + + + + + + + + + + + + + + 44100 + + + + + + + + + + + + + + 32000 + + + + + + + + + + + + + + mpeg 2.0 1 : samplerate / hz bitrate / kbit/s 8 16 24 32 40 48 56 64 80 96 112 128 144 160 24000 + + + + + + + + + + + + + + 22050 + + + + + + + + + + + + + + 16000 + + + + + + + + + + + + + + mpeg 2.5 1 : samplerate / hz bitrate / kbit/s 8 16 24 32 40 48 56 64 80 96 112 128 144 160 12000 + + + + + + + + + + + + + + 11025 + + + + + + + + + + + + + + 8000 + + + + + + + + + + + + + + 1 also all variable bitrate (vbr) formats are supported. note: 24.0 mhz internal clock (24.0 mhz external clock or 12.0 mhz external clock with clock- doubler) is enough for VS1011E to be able to decode all bitrates and sample rates with bass en- hancer and treble control active. version 1.04, 2007-10-08 26 vlsi solution y
VS1011E vs1011 e 8. functional description 8.2.4 supported riff wav formats the most common riff wav subformats are supported. format name supported comments 0x01 pcm + 16 and 8 bits, any sample rate 48 khz 0x02 adpcm - 0x03 ieee float - 0x06 alaw - 0x07 mulaw - 0x10 oki adpcm - 0x11 ima adpcm + any sample rate 48 khz 0x15 digistd - 0x16 digifix - 0x30 dolby ac2 - 0x31 gsm610 - 0x3b rockwell adpcm - 0x3c rockwell digitalk - 0x40 g721 adpcm - 0x41 g728 celp - 0x50 mpeg - 0x55 mpeglayer3 + for supported mp3 modes, see chapter 8.2.3 0x64 g726 adpcm - 0x65 g722 adpcm - version 1.04, 2007-10-08 27 vlsi solution y
VS1011E vs1011 e 8. functional description 8.3 data flow of VS1011E figure 13: data flow of VS1011E. first, depending on the audio data, mpeg or wav audio is received and decoded from the sdi bus. after decoding, if sci aiaddr is non-zero, application code is executed from the address pointed to by that register. for more details, see vs10xx application note: user applications. then data may be sent to the bass and treble enhancer depending on sci bass. after that the signal is fed to the volume control unit, which also copies the data to the audio fifo. the audio fifo holds the data, which is read by the audio interrupt (chapter 10.9.1) and fed to the sample rate converter and dacs. the size of the audio fifo is 512 stereo (2 16-bit) samples, or 2 kib. the sample rate converter converts all different sample rates to clki/512 and feeds the data to the dac, which in order creates a stereo in-phase analog signal. this signal is then forwarded to the earphone ampli?er. 8.4 serial data interface (sdi) the serial data interface is meant for transferring compressed mp3 audio data as well as wav data. also several different tests may be activated through sdi as described in chapter 9. version 1.04, 2007-10-08 28 vlsi solution y volumecontrol audiofifo s.rate.conv.and dac r bitstreamfifo sdi l sci_vol bassenhancer sb_amplitude=0sb_amplitude!=0 aiaddr = 0 aiaddr != 0 userapplication st_amplitude=0st_amplitude!=0 trebleenhancer mp1 / mp2 /mp3 / wav / adpcm decode 512 stereo samples
VS1011E vs1011 e 8. functional description 8.5 serial control interface (sci) the serial control interface is compatible with the spi bus speci?cation. data transfers are always 16 bits. VS1011E is controlled by writing and reading the registers of the interface. the main controls of the control interface are: 2 control of the operation mode, clock, and builtin effects 2 access to status information and header data 2 access to encoded digital data 2 uploading user programs 2 feeding input data 8.6 sci registers sci registers, pre?x sci reg type reset time 1 abbrev[bits] description 0x0 rw 0 70 clki 4 mode mode control 0x1 rw 0x2c 3 40 clki status status of VS1011E 0x2 rw 0 2100 clki bass built-in bass/treble enhancer 0x3 rw 0 80 xtali clockf clock freq + multiplier 0x4 rw 0 40 clki decode time decode time in seconds 0x5 rw 0 3200 clki audata misc. audio data 0x6 rw 0 80 clki wram ram write/read 0x7 rw 0 80 clki wramaddr base address for ram write/read 0x8 r 0 - hdat0 stream header data 0 0x9 r 0 - hdat1 stream header data 1 0xa rw 0 3200 clki 2 aiaddr start address of application 0xb rw 0 2100 clki vol volume control 0xc rw 0 50 clki 2 aictrl0 application control register 0 0xd rw 0 50 clki 2 aictrl1 application control register 1 0xe rw 0 50 clki 2 aictrl2 application control register 2 0xf rw 0 50 clki 2 aictrl3 application control register 3 1 this is the worst-case time that dreq stays low after writing to this register. the user may choose to skip the dreq check for those register writes that take less than 100 clock cycles to execute. 2 in addition, the cycles spent in the user application routine must be counted. 3 firmware changes the value of this register immediately to 0x28, and in less than 100 ms to 0x20. 4 when mode register write speci?es a software reset the worst-case time is 9600 xtali cycles. note that if dreq is low when an sci write is done, dreq also stays low after sci write processing. version 1.04, 2007-10-08 29 vlsi solution y
VS1011E vs1011 e 8. functional description 8.6.1 sci mode (rw) sci mode is used to control operation of VS1011E. bit name function value description 0 sm diff differential 0 normal in-phase audio 1 left channel inverted 1 sm layer12 allow mpeg layers i & ii 0 no 1 yes 2 sm reset soft reset 0 no reset 1 reset 3 sm outofwav jump out of wav decoding 0 no 1 yes 4 sm settozero1 set to zero 0 right 1 wrong 5 sm tests allow sdi tests 0 not allowed 1 allowed 6 sm stream stream mode 0 no 1 yes 7 sm settozero2 set to zero 0 right 1 wrong 8 sm dact dclk active edge 0 rising 1 falling 9 sm sdiord sdi bit order 0 msb ?rst 1 msb last 10 sm sdishare share spi chip select 0 no 1 yes 11 sm sdinew vs1002 native spi modes 0 no 1 yes 12 sm settozero3 set to zero 0 right 1 wrong 13 sm settozero4 set to zero 0 right 1 wrong when sm diff is set, the player inverts the left channel output. for a stereo input this creates a virtual surround, and for a mono input this effectively creates a differential left/right signal. sm layer12 determines whether it is allowed to decode mpeg 1 and 2 layers i and ii in addition to layer iii. if you enable layer i and layer ii decoding, you are liable for any patent issues that may arise. joint licensing of mpeg 1.0 / 2.0 layer iii does not cover all patents pertaining to layers i and ii. by setting sm reset to 1, the player is software reset. this bit clears automatically. when the user decoding a wav ?le wants to get out of the ?le without playing it to the end, set sm outofwav, and send zeros to vs1002e until sm outofwav is again zero. if the user doesnt want to check sm outofwav, send 128 zeros. if sm tests is set, sdi tests are allowed. for more details on sdi tests, look at chapter 9.7. version 1.04, 2007-10-08 30 vlsi solution y
VS1011E vs1011 e 8. functional description sm stream activates VS1011Es stream mode. in this mode, data should be sent with as even intervals as possible (and preferable with data blocks of less than 512 bytes), and VS1011E makes every attempt to keep its input buffer half full by changing its playback speed upto 5%. for best quality sound, the average speed error should be within 0.5%, the bitrate should not exceed 160 kbit/s and vbr should not be used. for details, see vs10xx application note: streaming. sm dact de?nes the active edge of data clock for sdi. if clear data is read at the rising edge, and if set data is read at the falling edge. when sm sdiord is clear, bytes on sdi are sent as a default msb ?rst. by setting sm sdiord, the user may reverse the bit order for sdi, i.e. bit 0 is received ?rst and bit 7 last. bytes are, however, still sent in the default order. this register bit has no effect on the sci bus. setting sm sdishare makes sci and sdi share the same chip select, as explained in chapter 7.2, if also sm sdinew is set. setting sm sdinew will activate vs1002 native serial modes as described in chapters 7.2.1 and 7.3.2. 8.6.2 sci status (rw) sci status contains information on the current status of VS1011E and lets the user shutdown the chip without audio glitches. name bits description ss ver 6:4 version ss apdown2 3 analog driver powerdown ss apdown1 2 analog internal powerdown ss avol 1:0 analog volume control ss ver is 0 for vs1001, 1 for vs1011, 2 for vs1002 and VS1011E, and 3 for vs1003. you can use sci mode to distinguish between vs1002 and VS1011E. after reset VS1011E has sm sdinew=0, while vs1002 has sm sdinew=1. ss apdown2 controls analog driver powerdown. normally this bit is controlled by the system ?rmware. however, if the user wants to powerdown VS1011E with a minimum power-off transient, turn this bit to 1, then wait for at least a few milliseconds before activating reset. ss apdown1 controls internal analog powerdown. this bit is meant to be used by the system ?rmware only. ss avol is the analog volume control: 0 = -0 db, 1 = -6 db, 3 = -12 db. this register is meant to be used automatically by the system ?rmware only. version 1.04, 2007-10-08 31 vlsi solution y
VS1011E vs1011 e 8. functional description 8.6.3 sci bass (rw) name bits description st amplitude 15:12 treble control in 1.5 db steps (-8..7, 0 = off) st freqlimit 11:8 lower limit frequency in 1000 hz steps (0..15) sb amplitude 7:4 bass enhancement in 1 db steps (0..15, 0 = off) sb freqlimit 3:0 lower limit frequency in 10 hz steps (2..15) the bass enhancer vsbe is a powerful bass boosting dsp algorithm, which tries to take the most out of the users earphones without causing clipping. vsbe is activated when sb amplitude is non-zero. sb amplitude should be set to the users preferences, and sb freqlimit to roughly 1.5 times the lowest frequency the users audio system can reproduce. for example setting sci bass to 0x00f6 will have 15 db enhancement below 60 hz. note: because vsbe tries to avoid clipping, it gives the best bass boost with dynamical music material, or when the playback volume is not set to maximum. it also does not create bass: the source material must have some bass to begin with. treble control vstc is activated when st amplitude is non-zero. for example setting sci bass to 0x7a00 will have 10.5 db treble enhancement at and above 10 khz. bass enhancer uses about 2.1 mips and treble control 1.2 mips at 44100 hz sample rate. both can be on simultaneously. 8.6.4 sci clockf (rw) sci clockf is used to tell if the input clock xtali is running at something else than 24.576 mhz. xtali is set in 2 khz steps. thus, the formula for calculating the correct value for this register is xt ali 2000 (xtali is in hz). values may be between 0..32767, although hardware limits the highest allowed speed. also, with speeds lower than 24.576 mhz all sample rates are no longer available. for example with 24 mhz clock 48 khz is played 2.5% off-key. setting the msb of sci clockf to 1 activates internal clock-doubling when the sample rate is next con?gured. note: sci clockf must be set before beginning decoding audio data; otherwise the sample rate will not be set correctly. example 1: for a 26 mhz clock the value would be 26000000 2000 = 13000 . example 2: for a 13 mhz external clock and using internal clock-doubling for a 26 mhz internal frequency, the value would be 0 x 8000 + 13000000 2000 = 39268 . example 3: for a 24.576 mhz clock the value would be either 24576000 2000 = 12288 , or just the default value 0 . for this clock frequency, sci clockf doesnt need to be set. version 1.04, 2007-10-08 32 vlsi solution y
VS1011E vs1011 e 8. functional description 8.6.5 sci decode time (rw) when decoding correct data, current decoded time is shown in this register in full seconds. the user may change the value of this register. however, in that case the new value should be written twice. sci decode time is reset at every software reset. 8.6.6 sci audata (rw) when decoding correct data, the current sample rate and number of channels can be found in bits 15:1 and 0 of sci audata, respectively. bits 15:1 contain the sample rate divided by two, and bit 0 is 0 for mono data and 1 for stereo. writing to this register will change the sample rate on the run to the number given. example: 44100 hz stereo data reads as 0xac45 (44101). example: 11025 hz mono data reads as 0x2b10 (11024). example: writing 0xac80 sets sample rate to 44160 hz, stereo mode does not change. 8.6.7 sci wram (rw) sci wram is used to upload application programs and data to instruction and data rams. the start address must be initialized by writing to sci wramaddr prior to the ?rst write/read of sci wram. as 16 bits of data can be transferred with one sci wram write/read, and the instruction word is 32 bits long, two consecutive writes/reads are needed for each instruction word. the byte order is big-endian (i.e. msbs ?rst). after each full-word write/read, the internal pointer is autoincremented. 8.6.8 sci wramaddr (rw) sci wramaddr is used to set the program address and memory bus for following sci wram writes/reads. sm wramaddr dest. addr. bits/ description start. . . end start. . . end word 0x1380. . . 0x13ff 0x1380. . . 0x13ff 16 x data ram 0x4780. . . 0x47ff 0x0780. . . 0x07ff 16 y data ram 0x8030. . . 0x84ff 0x0030. . . 0x04ff 32 instruction ram 0xc000. . . 0xffff 0xc000. . . 0xffff 16 i/o version 1.04, 2007-10-08 33 vlsi solution y
VS1011E vs1011 e 8. functional description 8.6.9 sci hdat0 and sci hdat1 (r) bit function value explanation hdat1[15:5] syncword 2047 stream valid hdat1[4:3] id 3 iso 11172-3 mpg 1.0 2 iso 13818-3 mpg 2.0 (1/2-rate) 1 mpg 2.5 (1/4-rate) 0 mpg 2.5 (1/4-rate) hdat1[2:1] layer 3 i 2 ii 1 iii 0 reserved hdat1[0] protect bit 1 no crc 0 crc protected hdat0[15:12] bitrate see bitrate table hdat0[11:10] sample rate 3 reserved 2 32/16/ 8 khz 1 48/24/12 khz 0 44/22/11 khz hdat0[9] pad bit 1 additional slot 0 normal frame hdat0[8] private bit not de?ned hdat0[7:6] mode 3 mono 2 dual channel 1 joint stereo 0 stereo hdat0[5:4] extension see iso 11172-3 hdat0[3] copyright 1 copyrighted 0 free hdat0[2] original 1 original 0 copy hdat0[1:0] emphasis 3 ccitt j.17 2 reserved 1 50/15 microsec 0 none when read, sci hdat0 and sci hdat1 contain header information that is extracted from mpeg stream being currently being decoded. right after resetting VS1011E, 0 is automatically written to both registers, indicating no data has been found yet. the sample rate ?eld in sci hdat0 is interpreted according to the following table: sample rate id=3 / hz id=2 / hz id=0,1 / hz 3 - - - 2 32000 16000 8000 1 48000 24000 12000 0 44100 22050 11025 the bitrate ?eld in hdat0 is read according to the following table: version 1.04, 2007-10-08 34 vlsi solution y
VS1011E vs1011 e 8. functional description layer i layer ii layer iii bitrate id=3 id=0,1,2 id=3 id=0,1,2 id=3 id=0,1,2 kbit/s kbit/s kbit/s 15 forbidden forbidden forbidden forbidden forbidden forbidden 14 448 256 384 160 320 160 13 416 224 320 144 256 144 12 384 192 256 128 224 128 11 352 176 224 112 192 112 10 320 160 192 96 160 96 9 288 144 160 80 128 80 8 256 128 128 64 112 64 7 224 112 112 56 96 56 6 192 96 96 48 80 48 5 160 80 80 40 64 40 4 128 64 64 32 56 32 3 96 56 56 24 48 24 2 64 48 48 16 40 16 1 32 32 32 8 32 8 0 - - - - - - when decoding a wav ?le, spi hdat0 and spi hdat1 read as 0x7761 and 0x7665, respectively. 8.6.10 sci aiaddr (rw) sci aiaddr indicates the start address of the application code written earlier with sci wramaddr and sci wram registers. if no application code is used, this register should not be initialized, or it should be initialized to zero. for more details, see vs10xx application note: user applications. 8.6.11 sci vol (rw) sci vol is a volume control for the player hardware. for each channel, a value in the range of 0..254 may be de?ned to set its attenuation from the maximum volume level (in 0.5 db steps). the left channel value is then multiplied by 256 and the values are added. thus, maximum volume is 0 and total silence is 0xfefe. example: for a volume of -2.0 db for the left channel and -3.5 db for the right channel: (4*256) + 7 = 0x407. note, that at startup volume is set to full volume. resetting the software does not reset the volume setting. note: setting sci vol to 0xffff will activate analog powerdown mode. 8.6.12 sci aictrl[x] (rw) sci aictrl[x] registers ( x=[0 .. 3] ) can be used to access the users application program. version 1.04, 2007-10-08 35 vlsi solution y
VS1011E vs1011 e 9. operation 9 operation 9.1 clocking VS1011E operates on a single, nominally 24.576 mhz fundamental frequency master clock. this clock can be generated by external circuitry (connected to pin xtali) or by the internal clock crystal interface (pins xtali and xtalo). also, 12.288 mhz external clock can be internally clock-doubled to 24.576 mhz. this clock is suf?cient to support a high quality audio output for all codecs, sample rates and bitrates, with bass and treble enhancers. 9.2 hardware reset when the xreset -signal is driven low, VS1011E is reset and all the control registers and internal states are set to the initial values. xreset-signal is asynchronous to any external clock. the reset mode doubles as a full-powerdown mode, where both digital and analog parts of VS1011E are in minimum power consumption stage, and where clocks are stopped. also xtalo and xtali are grounded. after a hardware reset (or at power-up), the user should set such basic software registers as sci vol for volume (and sci clockf if the input clock is anything else than 24.576 mhz) before starting decoding. 9.3 software reset in some cases the decoder software has to be reset. this is done by activating bit 2 in sci mode register (chapter 8.6.1). then wait for at least 2 1 s, then look at dreq. dreq will stay down for at least 6000 clock cycles, which means an approximate 250 1 s delay if VS1011E is run at 24.576 mhz. after dreq is up, you may continue playback as usual. if you want to make sure VS1011E doesnt cut the ending of low-bitrate data streams and you want to do a software reset, it is recommended to feed 2048 zeros to the sdi bus after the ?le and before the reset. version 1.04, 2007-10-08 36 vlsi solution y
VS1011E vs1011 e 9. operation 9.4 spi boot if gpio0 is set with a pull-up resistor to 1 at boot time, VS1011E tries to boot from external spi memory. spi boot rede?nes the following pins: normal mode spi boot mode gpio0 xcs gpio1 clk dreq mosi gpio2 miso the memory has to be an spi bus serial eeprom with 16-bit addresses (i.e. at least 1 kib). the serial speed used by VS1011E is 490 khz with the nominal 24.576 mhz clock. the ?rst three bytes in the memory have to be 0x50, 0x26, 0x48. the exact record format is explained in the application notes for vs10xx. if spi boot succeeds, sci mode is left with value 0x0800. 9.5 play/decode this is the normal operation mode of VS1011E. sdi data is decoded. decoded samples are converted to analog domain by the internal dac. if no decodable data is found, sci hdat0 and sci hdat1 are set to 0 and analog outputs are muted. when there is no input for decoding, VS1011E goes into idle mode (lower power consumption than during decoding) and actively monitors the serial data input for valid data. 9.6 feeding pcm data VS1011E can be used as a pcm decoder by sending to it a wav ?le header. if the length sent in the wav ?le is 0 or 0xfffffff, VS1011E will stay in pcm mode inde?nitely. 8-bit linear and 16-bit linear audio is supported in mono or stereo. 9.7 sdi tests there are several test modes in VS1011E, which allow the user to perform memory tests, sci bus tests, and several different sine wave tests. all tests are started in a similar way: VS1011E is hardware reset, sm tests is set, and then a test command is sent to the sdi bus. each test is started by sending a 4-byte special command sequence, followed by 4 zeros. the sequences are described below. version 1.04, 2007-10-08 37 vlsi solution y
VS1011E vs1011 e 9. operation 9.7.1 sine test sine test is initialized with the 8-byte sequence 0x53 0xef 0x6e n 0 0 0 0, where n de?nes the sine test to use. n is de?ned as follows: n bits name bits description f s idx 7:5 sample rate index s 4:0 sine skip speed f s idx f s 0 44100 hz 1 48000 hz 2 32000 hz 3 22050 hz 4 24000 hz 5 16000 hz 6 11025 hz 7 12000 hz the frequency of the sine to be output can now be calculated from f = f s s 128 . example: sine test is activated with value 126, which is 0b01111110. breaking n to its components, f s idx = 0 b 011 = 3 and thus f s = 22050 hz . s = 0 b 11110 = 30 , and thus the ?nal sine frequency f = 22050 hz 30 128 ? 5168 hz . to exit the sine test, send the sequence 0x45 0x78 0x69 0x74 0 0 0 0. note: sine test signals go through the digital volume control, so it is possible to test channels separately. 9.7.2 pin test pin test is activated with the 8-byte sequence 0x50 0xed 0x6e 0x54 0 0 0 0. this test is meant for chip production testing only. 9.7.3 memory test memory test mode is initialized with the 8-byte sequence 0x4d 0xea 0x6d 0x54 0 0 0 0. after this sequence, wait for 200000 clock cycles. the result can be read from the sci register sci hdat0, and one bits are interpreted as follows: version 1.04, 2007-10-08 38 vlsi solution y
VS1011E vs1011 e 9. operation bit(s) mask meaning 15 0x8000 test ?nished 14:7 unused 6 0x0040 mux test succeeded 5 0x0020 good i ram 4 0x0010 good y ram 3 0x0008 good x ram 2 0x0004 good i rom 1 0x0002 good y rom 0 0x0001 good x rom 0x807f all ok memory tests overwrite the current contents of the ram memories. 9.7.4 sci test sci test is initialized with the 8-byte sequence 0x53 0x70 0xee n 0 0 0 0, where n ? 48 is the register number to test. the content of the given register is read and copied to sci hdat0. if the register to be tested is hdat0, the result is copied to sci hdat1. example: if n is 48, contents of sci register 0 (sci mode) is copied to sci hdat0. version 1.04, 2007-10-08 39 vlsi solution y
VS1011E vs1011 e 10. VS1011E registers 10 VS1011E registers 10.1 who needs to read this chapter user software is required when a user wishes to add some own functionality like dsp effects to VS1011E. however, most users of VS1011E dont need to worry about writing their own code, or about this chapter, including those who only download software plug-ins from vlsi solutions web site. 10.2 the processor core vs dsp is a 16/32-bit dsp processor core that also had extensive all-purpose processor features. vlsi solutions free vskit software package contains all the tools and documentation needed to write, sim- ulate and debug assembly language or extended ansi c programs for the vs dsp processor core. vlsi solution also offers a full integrated development environment vside for full debug capabilities. 10.3 VS1011E memory map VS1011Es memory map is shown in figure 14. 10.4 sci registers sci registers described in chapter 8.6 can be found here between 0xc000..0xc00f. in addition to these registers, there is one in address 0xc010, called spi change. spi registers, pre?x spi reg type reset abbrev[bits] description 0xc010 r 0 change[5:0] last sci access address. spi change bits name bits description spi ch write 4 1 if last access was a write cycle. spi ch addr 3:0 spi address of last access. version 1.04, 2007-10-08 40 vlsi solution y
VS1011E vs1011 e 10. VS1011E registers figure 14: users memory map. 10.5 serial data registers sdi registers, pre?x ser reg type reset abbrev[bits] description 0xc011 r 0 data last received 2 bytes, big-endian. 0xc012 w 0 dreq[0] dreq pin control. version 1.04, 2007-10-08 41 vlsi solution y 0000 0000 stack stack instruction (32?bit) y (16?bit) x (16?bit) system vectors userspace y data rom x data rom 40006000 40006000 7000 7000 instruction rom hardware register space c000c100 c100 c000 0098 0098 1380 userspace 1400 13801400 1800 1800 userinstruction ram x data ram y data ram 0c00 0800 0780 07800800 0c00 0030 0030 0500 0500
VS1011E vs1011 e 10. VS1011E registers 10.6 dac registers dac registers, pre?x dac reg type reset abbrev[bits] description 0xc013 rw 0 fctll dac frequency control, 16 lsbs. 0xc014 rw 0 fctlh[4:0] clock doubler + dac frequency control msbs. 0xc015 rw 0 left dac left channel pcm value. 0xc016 rw 0 right dac right channel pcm value. every fourth clock cycle an internal 26-bit counter is added to by (dac fctlh & 15) 65536 + dac fctll. whenever this counter over?ows, values from dac left and dac right are read and a dac interrupt is generated. if dac fctl[4] is 1, the internal clock doubler is activated. 10.7 gpio registers gpio registers, pre?x gpio reg type reset abbrev[bits] description 0xc017 rw 0 ddr[3:0] direction. 0xc018 r 0 idata[3:0] values read from the pins. 0xc019 rw 0 odata[3:0] values set to the pins. gpio dir is used to set the direction of the gpio pins. 1 means output. gpio odata remembers its values even if a gpio dir bit is set to input. gpio registers dont generate interrupts. version 1.04, 2007-10-08 42 vlsi solution y
VS1011E vs1011 e 10. VS1011E registers 10.8 interrupt registers interrupt registers, pre?x int reg type reset abbrev[bits] description 0xc01a rw 0 enable[2:0] interrupt enable. 0xc01b w 0 glob dis[-] write to add to interrupt counter. 0xc01c w 0 glob ena[-] write to subtract from interript counter. 0xc01d rw 0 counter[4:0] interrupt counter. int enable controls the interrupts. the control bits are as follows: int enable bits name bits description int en sdi 2 enable data interrupt. int en sci 1 enable sci interrupt. int en dac 0 enable dac interrupt. note: it may take upto 6 clock cycles before changing int enable has any effect. writing any value to int glob dis adds one to the interrupt counter int counter and effectively disables all interrupts. it may take upto 6 clock cycles before writing to this register has any effect. writing any value to int glob ena subtracts one from the interrupt counter (unless int counter already was 0). if the interrupt counter becomes zero, interrupts selected with int enable are re- stored. an interrupt routine should always write to this register as the last thing it does, because in- terrupts automatically add one to the interrupt counter, but subtracting it back to its initial value is the responsibility of the user. it may take upto 6 clock cycles before writing this register has any effect. by reading int counter the user may check if the interrupt counter is correct or not. if the register is not 0, interrupts are disabled. version 1.04, 2007-10-08 43 vlsi solution y
VS1011E vs1011 e 10. VS1011E registers 10.9 system vector tags the system vector tags are tags that may be replaced by the user to take control over several decoder functions. 10.9.1 audioint, 0x20 normally contains the following vs dsp assembly code: jmpi dac_int_address,(i6)+1 the user may, at will, replace the instruction with a jmpi command to gain control over the audio interrupt. 10.9.2 sciint, 0x21 normally contains the following vs dsp assembly code: jmpi sci_int_address,(i6)+1 the user may, at will, replace the instruction with a jmpi command to gain control over the sci interrupt. 10.9.3 dataint, 0x22 normally contains the following vs dsp assembly code: jmpi sdi_int_address,(i6)+1 the user may, at will, replace the instruction with a jmpi command to gain control over the sdi interrupt. 10.9.4 usercodec, 0x0 normally contains the following vs dsp assembly code: jr nop if the user wants to take control away from the standard decoder, the ?rst instruction should be replaced with an appropriate j command to users own code. version 1.04, 2007-10-08 44 vlsi solution y
VS1011E vs1011 e 10. VS1011E registers unless the user is feeding mp3 data at the same time, the system activates the user program in less than 1 ms. after this, the user should steal interrupt vectors from the system, and insert user programs. 10.10 system vector functions the system vector functions are pointers to some functions that the user may call to help implementing his own applications. 10.10.1 writeiram(), 0x2 vs dsp c prototype: void writeiram(register i0 u int16 *addr, register a1 u int16 msw, register a0 u int16 lsw); this is the only supported way to write to the user instruction ram. this is because instruction ram cannot be written when program control is in ram. thus, the actual implementation of this function is in rom, and here is simply a tag to that routine. 10.10.2 readiram(), 0x4 vs dsp c prototype: u int32 readiram(register i0 u int16 *addr); this is the only supported way to read from the user instruction ram. this is because instruction ram cannot be read when program control is in ram. thus, the actual implementation of this function is in rom, and here is simply a tag to that routine. a1 contains the msbs and a0 the lsbs of the result. 10.10.3 databytes(), 0x6 vs dsp c prototype: u int16 databytes(void); if the user has taken over the normal operation of the system by switching the pointer in usercodec to point to his own code, he may read data from the data interface through this and the following two functions. this function returns the number of data bytes that can be read. version 1.04, 2007-10-08 45 vlsi solution y
VS1011E vs1011 e 10. VS1011E registers 10.10.4 getdatabyte(), 0x8 vs dsp c prototype: u int16 getdatabyte(void); reads and returns one data byte from the data interface. this function will wait until there is enough data in the input buffer. 10.10.5 getdatawords(), 0xa vs dsp c prototype: void getdatawords(register i0 y u int16 *d, register a0 u int16 n); read n data byte pairs and copy them in big-endian format (?rst byte to msbs) to d . this function will wait until there is enough data in the input buffer. version 1.04, 2007-10-08 46 vlsi solution y
VS1011E vs1011 e 11. vs1011 version changes 11 vs1011 version changes this chapter describes changes between different generations of vs1011. 11.1 changes between vs1011b and VS1011E, 2005-07-13 2 faster decoding: all codecs, bitrates and bass + treble controls can be used at clki = 24 mhz. 2 register sci bass now also has a treble control (chapter 8.6.3). loudness plugin not required. 2 can play ima adpcm in mono and stereo (chapter 8.2.4). 2 register space can now be written to with sci wram (chapter 8.6.7). 2 memory and register space can now be read from with sci wram (chapter 8.6.7). 2 added optional playback of mpeg 1 and 2 layers i and ii. (chapters 8.2.2, 8.2.1 and 8.6.1). 2 spi boot added (chapter 9.4). 2 mpeg 1, 2 and 2.5 layer iii decoding more robust against bit errors. 2 mpeg 2.5 decoding compatibility enhanced. 2 dreq goes down during sci operations. (chapter 7.4). 2 dreq goes down during memory test. (chapter 7.4). 2 in VS1011E the ss ver ?eld in sci status is 2. 2 also soic-28 is now a lead-free rohs-complian package. 11.2 migration checklist from vs1011b to VS1011E, 2005-07-13 2 the ss ver ?eld in sci status is 2. you can use sci status and sci mode to distin- guish between vs1002 and VS1011E. vs1011b has ss ver=1, sm sdinew=0, VS1011E has ss ver=2, sm sdinew=0, and vs1002 has ss ver=2, sm sdinew=1. 2 use built-in bass enhancer and treble control instead of the loudness plugin. the loudness plugin works, but the builtin controls are much faster. version 1.04, 2007-10-08 47 vlsi solution y
VS1011E vs1011 e 12. document version changes 12 document version changes this chapter describes the most important changes to this document. 12.1 version 1.04 for VS1011E, 2007-10-08 2 starting from VS1011E also soic-28 is a rohs-compliant lead-free package. 12.2 version 1.03 for VS1011E, 2005-09-05 2 production version, no longer preliminary 12.3 version 1.02 for VS1011E, 2005-07-13 2 new features for VS1011E added (see chapter 11.1). 12.4 version 1.01 for vs1011b, 2004-11-19 2 removed non-existing scimb powerdown bit. 2 added soic-28 package to chapters 5.1.3 and 5.2.2. 12.5 version 1.00 for vs1011b, 2004-10-22 2 fully quali?ed values to tables in chapter 4. 2 reassigned bga-49 balls for pins dvdd2, dgnd2 and dgnd3 in chapter 5.2. 12.6 version 0.71 for vs1011, 2004-07-20 2 added instructions to add 100 k pull-down resistor to unused gpios to chapter 5.2. 12.7 version 0.70 for vs1011, 2004-05-13 2 removed sm jump. 12.8 version 0.62 for vs1011, 2004-03-24 2 rewrote and clari?ed chapter 8.2, supported audio codecs. version 1.04, 2007-10-08 48 vlsi solution y
VS1011E vs1011 e 13. contact information 13 contact information vlsi solution oy entrance g, 2nd ?oor hermiankatu 8 fin-33720 tampere finland fax: +358-3-3140-8288 phone: +358-3-3140-8200 email: sales@vlsi.? url: http://www.vlsi.?/ version 1.04, 2007-10-08 49 vlsi solution y

▲Up To Search▲

Price & Availability of VS1011E

	To Download VS1011E Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .